1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus suitable for testing semiconductor devices such as semiconductor integrated circuits, and more particularly, to a semiconductor device testing apparatus having an output voltage corrective circuit of the type that corrects, by digital processing, a voltage of a test signal to be applied to a semiconductor device under test (semiconductor device under test, commonly called DUT) and outputs the corrected voltage.
2. Description of the Related Art
A semiconductor device testing apparatus (commonly called an IC tester) for testing a semiconductor device, specifically, a semiconductor integrated circuit (hereinafter referred to as IC) which is a typical example of semiconductor devices, has in its body (commonly called main frame) a various kinds of circuits of the testing apparatus that generate a test signal of a predetermined pattern to be applied to an IC to be tested (IC under test), an address signal, a control signal and so forth for application to the IC under test, and receive and process response signals from the IC under test to measure their electric characteristics. A test head (commonly called pin electronics) of the testing apparatus, which applies the test signal of a predetermined pattern, the address signal, the control signal and so forth to the IC under test, and receives response signals therefrom, is placed at a distance from the main frame (for example, at a test section of a semiconductor device transporting and handling apparatus commonly called handler which transports a semiconductor device for testing, and handles or processes the tested semiconductor device on the basis of the test results). The test head has a socket mounted thereto, with which the IC is brought into electrical contact when a predetermined test is performed.
While the semiconductor device testing apparatus will hereinbelow be described as being applied to testing of ICs which are a typical example of semiconductor devices for brevity of description, it is needless to say that the semiconductor device testing apparatus of this kind can be used to test other semiconductor devices than IC as well.
As is well known in the art, an IC to be tested has a number of terminals (leads) or pins and the semiconductor device testing apparatus (hereinafter referred to as IC tester) carries out testing of the IC by applying a test signal of a predetermined pattern to each of the pins of the IC under test (DUT). To this end, the IC tester and each pin of the DUT (in practice, each terminal of the socket to which the DUT is mounted) are electrically connected to each other via an independent or separate electrical path (including a circuit or circuits). Usually, the path between the IC tester and each pin of the DUT is called a channel.
The voltage of a test signal, which is applied to each of the pins of a DUT, often differs from the voltage value set in the IC tester due to variations in the characteristics, values, or the like of individual elements forming respective paths, or owing to various other causes. Hence, it is necessary that voltages of test signals to be applied to the pins of a DUT be corrected in compensation for variations or the like in respective paths.
An example of this kind of prior IC tester is illustrated in FIGS. 9 and 10. FIG. 9 shows the configuration of the pertinent part of the circuits of the IC tester housed in its main frame, and FIG. 10 shows a test head of the IC tester and an IC under test (DUT).
As shown in FIG. 9, the IC tester of this example has in its main frame an offset memory 1, a gain memory 2, a plurality of RON output level registers 3, an output level selection register 4, a tester processor 5, a first, a second and a third digital-to-analog (D/A) converters 6, 7 and 8, a selector 9, an analog selector 10, a refresh capacitor 11, a plurality of RON/ROF selection register 15, an RON/ROF selector 16, an ROF data register 17, and a refresh sequencer 18.
As depicted in FIG. 10, there is provided in the test head a driver 13 for applying a test signal to each of the pins of a DUT 14. Although only one driver 13 is shown in FIG. 10, the number of such drivers is equal to the number of pins of the DUT 14, and accordingly, the number of channels. The main frame and the test head are electrically connected via cables 12 (only one cable 12 is shown in FIG. 10, but the number of such cables is equal to the number of channels), and the output voltage from each driver 13 is applied to the corresponding pin of the DUT 14 via a cable and an IC socket not shown.
In the offset memory 1 there is prestored (previously stored) offset data contained in data that is used to compensate for variations of the channels to the respective pins of the DUT. In the gain memory 2 there is prestored gain data also contained in the immediately mentioned data. These offset and gain data will be described later on.
The number of RON output level registers 3 used is set to the same number as that of several kinds of independent voltage values of test signals to be applied to DUTs, and the voltages of different values are stored in the corresponding RON output level registers, respectively. When only one kind of voltage value, for example, 3 V is applied to the DUTs, one RON output level register may suffice to test them. In general, however, a plurality of RON output level registers are provided so that a required kinds of set voltage values can be stored in selected ones among them, respectively. Thus, the voltage values corresponding in number to the RON output level registers 3 can be set. Since the illustrated example is provided with eight RON output level registers 3, it is possible to set up to eight independent voltage values to be applied to the DUTs. These voltage values are set by a test program.
The output level selection register 4 stores therein select information for determining which voltage value among the voltage values stored in the RON output level registers 3 is to be allocated to the corresponding one of the pins of each DUT, and accordingly the channels thereto. The RON/ROF selection registers 15 each store therein select information for determining whether to output the set voltage stored in the corresponding RON output level register 3 (an RON state) or to output the set voltage stored in the ROF data register 17 (an ROF state). Accordingly, the number of RON/ROF selection registers 15 is the same as that of the RON output level registers 3. Since in this example eight RON output level registers 3 are provided, the number of RON/ROF selection registers 15 used is also eight. These select information stored in the selection registers 4 and 15 are set by the test program.
What is meant by the term "RON state" is to turn on (ON) the voltage set in the RON output level register 3, that is, refers to an operation by which the voltage set in the RON output level register 3 is outputted therefrom. The term "ROF state" is intended to refer to an operation by which the voltage set in the RON output register 3 is turned off (OFF) and 0 V of the initial voltage value is outputted from the ROF data register 17.
The tester processor 5 is a central processing unit (CPU) which exerts centralized control over the whole IC tester including peripheral equipment, and it responds to instructions of the test program to provide predetermined data, voltages and select information to the offset memory 1, the gain memory 2, the RON output level registers 3, the output level selection register 4, and the RON/ROF selection registers 15.
The ROF data register 17 stores therein 0 V as a fixed value that is a set voltage outputted in the ROF state.
The refresh sequencer 18 generates a sequence of serial data generation and processing, and sequentially controls the offset memory 1, the gain memory 2, and the output level selection register 4.
The refresh sequencer 18 is always in operation since the voltage corrected for each channel to be applied to the corresponding one of the pins of the DUT 14 needs to be charged in the refresh capacitor 11 in each channel at all times. The offset memory 1, the gain memory 2 and the output level selection register 4 operate in accordance with the sequence generated by the refresh sequencer 18 and sequentially output respective signal data for each channel. The offset data prestored in the offset memory 1 and the gain data prestored in the gain memory 2 are inputted into the first D/A converter 6 and the second D/A converter 7 where they are converted into analog data, respectively. The output from the second D/A converter 7 is inputted via an amplifier amp2 into a terminal vref (reference voltage terminal) of the third D/A converter 8 to correct its reference voltage vref, namely, its gain.
Either the output data of each RON output level register 3 which is the test signal to be fed to the DUT 14 or the output data of the ROF data register 17 with the fixed voltage of 0 V stored therein is selected by the RON/ROF selector 16 in response to a select signal that is provided thereto from the corresponding RON/ROF selection register 15. The voltage data selected by the RON/ROF selector 16 is fed to the selector 9. Responding to a select signal fed thereto from the output level selection register 4, the selector 9 selects the channel over which the received voltage data is to be sent. In this way, the RON/ROF voltage data for each channel specified by the test program is outputted from the selector 9. This voltage data is inputted into the third D/A converter 8 where it is converted into analog data.
The analog voltage data outputted from the first D/A converter 6 is provided via an amplifier amp1 to an inverting input terminal of another amplifier amp3 subsequent thereto and the analog voltage data outputted from the third D/A converter 8 is provided to a non-inverting input terminal of the amplifier amp3, wherein they are added to each other or subtracted one from the other in analog form. The output from the amplifier amp3 is inputted as corrected analog voltage data into the analog selector 10 which converts the inputted serial data to parallel data corresponding to the individual channels and outputs a corrected analog voltage to each channel.
It is arranged that the analog voltage outputted from the analog selector 10 charges the refresh capacitor 11 in each channel, which holds it while a different channel is being selected.
Since the main frame and the test head are electrically connected via the cables 12 as mentioned previously, the voltage charged in the refresh capacitor 11 of each channel is amplified by an amplifier amp4 and then applied via the associated cable 12 to the corresponding driver 13 provided in the test head. The output of each driver 13 is connected to the corresponding terminal of an IC socket (not shown) mounted on the test head. Therefore, when the DUT 14 is brought into electrical contact with the IC socket, the output voltage is applied as a test voltage to each pin of the DUT 14 from the driver 13 corresponding thereto.
It is most desirable that the above-described voltage generator circuit (including the driver 13) of each channel, which generates the voltage for test to be applied to the DUT, be configured so that its output voltage characteristic with respect to the voltage value set in the corresponding RON output level register 3 (the output voltage characteristic of the driver 13) offers or exhibits a linear equation of the coefficient 1. Though linear circuit elements are used as circuit elements forming the respective voltage generator circuits of respective channels, in practice, there are many cases that each voltage generator circuit (driver 13) does not necessarily exhibits its output voltage characteristic which is represented by a linear equation of the coefficient 1 with respect to the set voltage due to variations in circuit elements, or owing to various other causes. Therefore, by merely setting the applied voltage to the DUT or the driver output voltage, the output voltage of each voltage generator circuit can seldom come to the set value. For this reason, it is customary in the art to always correct the set voltage outputted from the RON output level register 3 so that the output voltage characteristic of the voltage generator circuit of each channel exhibits a linear equation of the coefficient 1 and thereafter a test for DUTs is performed by applying the corrected voltage for test to the DUTS.
This will be described below in more detail. If the relationship between the output voltage of the voltage generator circuit of each channel, that is, the output voltage Y of the driver 13 at the last stage and the set voltage X of, the RON output level register 3 exhibits the following linear equation EQU X=Y
then the output voltage characteristic of the voltage generator circuit of each channel will come to the linear equation of the coefficient 1 as indicated by the solid line in FIG. 8. As a result, the proper output voltage can be obtained from the driver by merely setting the driver output voltage. Practically, in most instances, however, the relationship between the output voltage Y of the driver 13 at the last stage and the set voltage X exhibits the following linear equation EQU Y=BX+C
as indicated by the broken line in FIG. 8 owing to variations in the circuit elements used or various other causes. In the above, B is a coefficient and C is a constant. For example, when the set voltage is 3 V, the output voltage of 3 V will be obtained with respect to the set voltage of 3 V if the driver 13 has such an output voltage characteristic as indicated by the solid line in FIG. 8. Since the actual driver output voltage characteristic will become Y=BX+C due to the differences in characteristic, value or the like between the circuit elements or for some other reasons, an output voltage of only 2.5 V or so, for instance, can be obtained. It is therefore necessary to make corrections in which the coefficient B becomes 1 and the constant C becomes 0 so as to obtain the output voltage of 3 V.
Even if the voltage generator circuits of respective channels have exactly the same circuit configuration, the values of the coefficient B and the constant C often differ between channels due to the variation in the circuit elements used or owing to various other causes. Therefore, corrections of the values of the coefficient B and the constant C must be made for each channel so that an output voltage of each channel becomes the set voltage. The offset data prestored in the offset memory 1, which is contained in the data for compensating for the variations of the circuit elements of each channel, corresponds to the above-mentioned constant C, and the gain data prestored in the gain memory 2 corresponds to the above-mentioned coefficient B.
Next, a description will be given of a method for correcting the driver output voltage in a conventional IC tester of the above configuration.
First, the RON output level registers 3 are put in the ROF state and the zero volt set in the ROF data register 17 is selected and provided via the analog selector 10 to the corresponding channel. The output voltage from the driver 13 of the test head at this time is measured. This measured value is used as offset data (C in the equation of the broken line in FIG. 8), and hence it is stored in the offset memory 1. Next, the RON output level registers 3 are put in the RON state and an arbitrary set voltage is selected and provided via the analog selector 10 to the same channel. The output voltage from the driver 13 of the test head at this time is also measured. Based on the ideal value in this case (an arbitrary set voltage) and the measured value, gain data is calculated by the test processor 5 so that the set voltage is obtained from the driver 13. The gain data thus obtained is stored in the gain memory 2.
Since the gain and offset data are unique or inherent values of each pin of the DUT, the above operation is repeated for each channel and the offset data of each channel is stored in the offset memory 1 and the gain data in the gain memory 2, respectively.
During testing the offset memory 1, the gain memory 2 and the output level selection register 4 are sequentially controlled by the refresh sequencer 18. The gain memory 2 is thus accessed, from which the corrected gain data is fed via the second D/A converter 7 and the amplifier amp2 to the terminal vref of the third D/A converter 8 to set its reference voltage Vref based on the corrected gain data. By this, the reference voltage Vref of the third D/A converter 8 (and consequently the slope of the output voltage characteristic in FIG. 8) is altered in an analog quantity. The corrected offset data is read out of the offset memory 1 and fed via the first D/A converter 6 and the amplifier amp1 to the amplifier amp3 for analog addition to or subtraction from the corrected set analog voltage that is provided from the third D/A converter 8.
Output voltages thus corrected by analog processing for all channels CH1 to CHn are sequentially outputted from the analog selector 10, then the refresh capacitors 11 of all the channels are charged one after another, and the charged voltages are supplied to the drivers 13 of the test head for application to the respective pins of the DUT.
FIG. 11 is a timing chart showing the operation sequence described above. In this example, three kinds of voltages of 3 V (HIN1), 2 V (HIN2) and 1 V (HIN3) are set in three of the output level registers 3, respectively, and the set voltages are selected by a test program in the order of 3 V.fwdarw.1 V.fwdarw.2 V.fwdarw.3 V .fwdarw.. . . 3 V.fwdarw.1 V.fwdarw.2 V.fwdarw.3 V for the channels CH1 through CHn. Further, this example shows the case that select information is inputted into the RON/ROF selection registers 15 from the test program so as to select the set voltages of 3 V (HlN1) and 2 V (HIN2) and so as not to select the set voltage of 1 V (HIN3) and hence so as to select ROF (0 V). Thus, the set voltages are outputted from the analog selector 10 to the channels CH1 through CHn in the order of 3 V.fwdarw.0 V.fwdarw.2 V.fwdarw.3 V.fwdarw. . . . 3 V.fwdarw.0 V.fwdarw.2 V.fwdarw.3 V.
Since the conventional IC tester has a construction which charges and holds the corrected output voltage in the refresh capacitor 11, a refresh circuit is naturally needed to hold the voltage. The refresh circuit is always in operation during testing the operation of the DUT, and hence there is a drawback that the refresh circuit interferes with other circuits of the IC tester, which results in deterioration of the accuracy of the test for the operation of the DUT.
Another problem of the prior art lies in that charging the refresh capacitor 11 is time-consuming since it has a time constant. On this account, as indicated by the waveform in the prior art shown in FIG. 12(A), the refresh capacitor 11 is not charged up to the set voltage level on only a single charge over one refresh cycle period during the RON/ROF state, and hence it has a drawback that its settling time is long. That is, it requires much time for the charged voltage of the refresh capacitor 11 to reach the set voltage level and become stable, and hence there is a disadvantage that the time duration of the test is lengthy.
Further, since the refresh circuit charges the capacitors 11 of the respective channels in a sequential order (i.e. serially), charged voltages in all the channels do not rise up at the same timing and a time delay occurs for each channel. The time delay from the time point that the capacitor of the first channel is fully charged to the time point that the capacitor of the last channel is fully charged increasing more and more as the number of channels is increased. When the time delay is increased, it is difficult to simultaneously apply test signals (voltages for test) to all the pins of the DUT with a predetermined delay after the application of the power supply voltage to the DUT. As will be understood from the waveform in the prior art shown in FIG. 7(A), after the application of the power supply voltage to the DUT, the channel CH1 rises up after a time interval tb has passed, but a time interval tc is required until the channel CHn rises up after the channel CH1 has risen. For this reason, it is difficult to simultaneously apply voltage signals for test to all the pins of the DUT unless the time delay of tc is given. As stated above, the time delay tc is increasing more and more as the number of channels is increased. Accordingly, since every IC is supplied with voltages its all terminal pins at the same time in its actual use, there is a disadvantage that the test corresponding to the actual use of an IC cannot be performed.
Another disadvantage of the conventional IC tester is that a large-scale corrective circuit must be used for correcting the set voltages because the set voltages are corrected through analog processing. Since it is hard to place such a large-scale circuit in the test head of a multi-channel configuration, it is general practice in the prior art to connect the main frame and the test head via a large number of cables for the transmission of voltage signals. This requires a cable for each channel, and hence the large amount of cables must be used.
Besides, if it is wanted to test a DUT with a different set voltage applied to a particular one or more of the pins of the DUT from the remaining pins thereof, it is necessary in the prior art to alter or modify the test program since a distinct independent setting cannot be made. Accordingly, this is time-consuming and troublesome.